1. Field Of the Invention
The present invention relates to integrated circuits, and is more particularly concerned with integrated circuits having III-V heterobipolar transistors (HBT), in which planar transistors are desirable for a simple, reliable and structure-conforming connection. At the same time, requirements for highest switching speed are raised. What is particularly required of the design of the heterobipolar transistor is a minimum base-collector (B-C) boundary surface, i.e. a minimization of the parasitic B-C region. The contributions to the transit time in the transistor that, by now, are significant, in particular, the collector charging time and the emitter charging time, can be greatly reduced with this measure.
2. Description of the Prior Art
In non-self-aligned HBT processes or, respectively, in those processes having only a self-aligned base-emitter complex, an additional parasitic B-C surface arises that is established by length times spacing between the emitter and the collector or, respectively, between the base and the collector. The problem of obtaining a minimum B-C remains unresolved in these heterobipolar transistors. In this connection, one may take reference to, for example, the K. C. Wang, et al article "A 4-bit Quantizer Implemented with AlGaAs/GaAs Heterojunction Bipolar Transistors," GaAs IC-Symposium, Technical Digest, 1987, pp. 83-86, the Mau-Chung F. Chang, et al article "AlGaAs/GaAs Heterojunction Bipolar Transistors Fabricated Using a Self-Aligned Dual-Lift-Off Process", IEEE Electron Device Letters, Vol. EDL-8, No. 7 July 1987, pp. 303-305, the Kouhei Morizuka, et al article "AlGaAs/GaAs HBT's Fabricated by a Self-Alignment Technology, Using Polyimide for Electrode Separation", IEEE Electronic Device Letters, Vol. 9, No. 11, November 1988, pp. 598-600, and the K. Morizuka, et al article "Transit-Time Reduction in AlGaAs/GaAs HBT's utilizing Velocity Overshoot in the p-type Collector Region", IEEE Electron Device Letters, Vol. 9, No. 11, November 1988, pp. 585-587.
Another approximation is a totally self-aligned HBT wherein the emitter and the base, as well as the base and the collector or, respectively, the emitter and the collector are separated from one another by the interposition of insulating spacer layers that are less than 1 .mu.m wide. The processes that have been set forth up to this point in the publications end in a double mesa structure that respectively combines the emitter and the base or, the base and the collector and has a pronounced surface topography. In this respect, one may refer to the Sadao Adachi, et al article "Collector-Up HBT's Fabricated by Be.sup.+ and O.sup.+ Ion Implantations", IEEE Electron Device Letters, Vol. EDL-7, No. 1, January 1986, pp. 32-34, the Mohammad Madihian, et al article "Fabrication and Modeling of a Novel Self-Aligned AlGaAs/GaAs Heterojunction Bipolar Transistor with a Cutoff Frequency of 45 GHz", IEEE IEDM, 1986, pp. 270-273, and the Y. Ota, et al article "AlGaAs/GaAs HBT with GaInAs Cap Layer Fabricated by Multiple-Self-Alignment Process Using One Mask", Electronics Letters, Vol. 25, No. 9, April 1989, pp. 610-612.